The authors present a time-to-digital converter based on multi-stage amplification structure. This structure consists of coarse stage and fine stage. Coarse stage utilizes delay line to get the residue which is less than a buffer’s delay. A small area and low power residue selecting logic is designed. In the fine stage, 2× time amplifier and half judger is utilized to generate 4 binary codes from MSB to LSB. Simulation in SMIC 65 nm process shows that the new structure has a high conversion speed up to 470 MS/s and power consumption is 1.3 mW at 100 MHz with the resolution of 1.44 ps and range of 736 ps. An accurate gain robust to PVT variation can be achieved with the calibration of the time amplifier, so a good integral nonlinearity is obtained.